Summary of Integrated RF-CMOS Transceivers challenge RF Test Validation

Integrated RF-CMOS Transceivers challenge RF Test Validation is a paper from the 2006 IEEE International Test Conference and I read it.

The author is Frank Demmerle

Before I begin I would like to extend my apologies to the author of this paper if I completely mangle his work in my summary of it.

Summary

The first part of this paper discusses how RF systems are being consolidated into a single chip with the advent of RF functions being implemented in CMOS technology. Base-band analog functions have been in CMOS for a long time, but RF had required a mixture of RF and CMOS. As the RF circuits migrate entirely to CMOS these functions can be combined to a single chip.

This poses a problem for test as the interface between the RF and base-band analog chips provided an access point for RF testing. While the trend may be towards a single chip there are still many systems that have the digital portion (DSP) separate from the analog/RF and they are connected by a digital only interface.

This again is a problem for test because now the only access point for an RF ATE is a high speed digital interface, and an RF ATE typically cannot handle such high speed communication without very expensive upgrades.

Modulation Testing

These RF chips transmit data by modulation the data with a carrier signal. The modulation signal is generated by a voltage controlled oscillator (VCO). The VCO frequency is controlled by a phase-locked loop (PLL). The quality of the output transmitted signal is highly dependent on this VCO circuit. Traditionally the way to test the modulation circuit was to source I and Q signals from the ATE to the DUT and look at the frequency content of the output transmitted signal. I and Q are (I think I got this right) two signals that are out of phase by 90 degrees. So, you can just use a sine and cosine signals.

The trouble comes in here when you implement the RF circuit entirely in CMOS the architecture changes to a polar modulator and the sine/cosine stimulus doesn’t work.

Since the VCO is so important to the modulation (specifically the gain and linearity) there is often built in circuitry to tune the VCO itself, this is called self-alignment of the PLL. Since the gain and linearity of the VCO are so important to the operation of the system these parameters needs to be tested. The way the VCO would typically be tested is to apply a number of input voltages and measure the output frequency. The self-alignment circuit allows a DFT type capability since the self-alignment has to measure frequency as part of its operation and thus that frequency measurement can be utilized for test purposes. The author goes on to talk about how this test method is much faster and more accurate than an external frequency measurement would be.

System Tests

The author then explains how additional system level testing is necessary beyond the self-alignment DFT test described above. Tests like phase noise testing/phase error testing, modulation mask test/adjacent channel power rejection test (ACPR) and error vector magnitude (EVM) are typical system level RF tests. However, these tests can be complex, slow and require expensive equipment. They may be necessary if there is a lack of test access to smaller lower level circuit blocks.

Digital Interface

As I mentioned before, some RF chips may have only a high speed digital interface that requires very expensive RF ATE hardware to access. One possible solution to this, the author discusses, is putting an FPGA in-between the RF chip and the ATE to buffer those high-speed digital signals. What that would do is the FPGA could run at high speed to communicate with the RF chip and parallelize data to a lower data rate the ATE can deal with. The FPGA could also be utilized to do specialized processing of data best handled by an FPGA processor, like an FFT or other signal processing tasks.

My Takeaway

I want learn more about RF testing in general and this paper gave me some idea about what seems to be some common RF chip testing tasks. This paper is a few years old and I wonder if some of the ATE abilities, such as working with high-speed digital interfaces have improved and gotten cheaper. I also wonder to what extent the RF and digital chips have been combined into one chip, which would make these methods less applicable. This paper was well written and I learned a lot.